1. Field of the Invention
The present invention relates in general to multiple-bit digital-to-analog encoders (DACs) and in particular, to a spectral shaping dynamic encoder for a DAC.
2. Description of Related Art
Delta-Sigma ADC Architecture
FIG. 1 depicts a prior art delta-sigma analog-to-digital converter (ADC) 10 including a sample and hold (S/H) circuit 12, a delta-sigma modulator 14, and a digital decimator 16, for digitizing an analog input signal AIN to produce an output data sequence D representing the analog input signal. S/H circuit 12 samples the AIN signal on each pulse of a clock signal (CLOCK) at a rate much higher than the AIN signal bandwidth to produce a sequence of discrete analog samples a[n] supplied as input to delta-sigma modulator 14. Delta-sigma modulator 14 responds to each pulse of the CLOCK signal by generating an element of arm M-bit wide output sequence x[n]. When each element of the x[n] sequence is, for example, M=1 bit wide, delta-sigma modulator 14 sets the x[n] bit to a logical 1 increasingly more frequently than to a logical 0 as AIN increases in magnitude so that the density of 1's in the x[n] sequence is proportional to the magnitude of AIN. When the x[n] sequence is more than one bit, delta-sigma modulator 14 generates higher values of x[n] more frequently as AIN increases. Decimator 16, a finite impulse response (FIR) filter, filters the x[n] X sequence to produce an N-bit wide sequence of elements       d    ⁡          [      n      ]        =            ∑              i        =                  -          N1                    N2        ⁢                   ⁢                  f        ⁡                  [          i          ]                    ·              x        ⁡                  [                      n            -            i                    ]                    where N1 and N2 are integers and FIR filter coefficients f[−N1]−f[N2] are numbers selected to give decimator 16 selected low pass or band pass characteristics to eliminate aliasing and out-of-band quantization noise. N is much larger than M. A down sampler 17 reduces the number of elements of the d[n] sequence by some factor p to produce an N-bit wide output sequence D. Thus, only every pth element of sequence d[n] sequence becomes an element of sequence D.
FIG. 2 is a timing diagram illustrating a simple example wherein p=3, i has values of the set {−1,0,1}, and all filter coefficients f[−1]=f[0]=f[1]=1. Thus in this example each element of sequence D is equal to a sum of a separate set three elements of the x[n] sequence, although in practice filter coefficients f will often have other values to provide a desired low pass or band pass filter characteristic.
Assume ADC 10, for example has an input range of 0-3 volts, and that as shown in FIG. 2, AIN signal ramps linearly from 0 to 3 volts during 36 CLOCK signal cycles. Signal x[n] step-wise approximates the AIN signal. The density of l's represented by signal x[n] increases with the magnitude of x[n]. In this simple example, decimator 16 sums the preceding three x[n] sequence bits to produce each element of the d[n] sequence. In the example of FIG. 2, the output sequence D of ADC 10 represents input signal magnitude AIN with 2-bit resolution because the 2-bit wide elements of the D sequence can be any of 22 values of the set {0,1,2,3}. We can increase the resolution of ADC 10 by increasing p. For example, when decimator 16 sums x[n] sequence elements during p=255 clock cycles, then elements of sequence D would be 8-bits wide and would represent 28 different signal magnitudes. However, to avoid aliasing, the CLOCK signal frequency should be at least p times the Nyquist frequency of the AIN signal.
Delta-sigma modulator 14 includes an analog summer 18, an analog filter 20 having a suitable discrete transfer function H(z), an M-bit ADC converter 22, and an M-bit digital-to-analog converter 24. Filter 20 filters the output signal b[n] of summer 18 to produce a signal c[n] and ADC 22 digitizes signal c[n] to produce the modulator output signal x[n]. For example when M=1, and c[n] is above a threshold level, ADC 22 sets x[n] to a 1, and otherwise sets x[n] to a 0 when c[n] is below the threshold level. DAC 24 drives its analog output signal y[n] to the maximum expected level of x[n] when x[n] is a 1 and drives y[n] to the minimum expected level of x[n] when x[n] is a 0. The feedback loop formed by devices 18-24 tries to keep c[n] at the threshold level of ADC 22 by driving x[n] to a 1 with a frequency that increases with the amplitude of AIN. Modulator 14 operates in a generally similar manner when M>1 except that ADC 22 and DAC 24 adjust x[n] and y[n] with M-bit resolution.
Spectral Shaping
The feedback provided by DAC 24 spectrally shapes quantization errors of ADC 22 so that the errors mostly appear as high frequency components of x[n] outside the frequency range of x[n] and outside the pass band of decimator 16 so that the decimator can remove those spectrally shaped, out-of-band quantization errors. However, the feedback loop may not correct errors arising from any non-linearity of DAC 24. Ideally the output y[n] of DAC 24 should be a linear function of its input x[n] to avoid error components in y[n] within the pass band of decimator 16. Single-bit (M=1) delta-sigma data converters are popular because their 1-bit internal DACs are inherently linear, but a 1-bit data converter can achieve only relatively limited resolution for a given over-sampling ratio p. Sigma-delta modulator employing 1-bit DACs are also sensitive to timing errors such as sampling clock jitter and to other sources of error.
Multiplebit (M>1) DACs are not inherently linear, yet a higher resolution delta-sigma data converters can employ multiple-bit DACs by using “mismatch-shaping” to resolve problems associated with their nonlinear behavior. The nonlinearity of a multiple-bit DAC arises from mismatches in its internal components, and while a “mismatch-shaping” DAC exhibits nonlinear behavior, it shapes the error component frequencies of its output signal resulting from component mismatches so that they reside outside a frequency band of interest. Thus, when DAC 24 of FIG. 1 is a mismatch-shaping DAC, the frequency components of its output signal y[n] and of the output signal x[n] of delta-sigma modulator 14 resulting from the non-linear behavior of DAC 24 reside outside the frequency band of input signal a[n]. Decimator 16 can therefore filter those frequency components out of x[n], leaving data signal d[n] unaffected by the non-linear behavior of DAC 24.
FIG. 3 depicts a typical prior art mismatch-shaping DAC 24 for converting a nine-level (3+ bit) input binary word x[n] into a nine-level output signal y[n]. The quantity n is a discrete time index. A dynamic digital encoder 20 converts data each nth incoming word x[n] into an 8-bit outgoing word {x1[n] . . . x8[n]} wherein the number of bits of word {x1[n] . . . x8[n]} that are I's matches the value of input data word x[n]. A set of eight 1-bit DACs 30 converts each bit x1[n] . . . x8[n] into a corresponding analog signal y1[n] . . . y8[n], each residing at a high or low level depending on whether its corresponding data bit x1[n] . . . x8[n] is a 1 or a 0. A summing amplifier 31 sums the eight analog signals y1[n] . . . y8[n] to produce an analog output signal y[n] that may reside at any of nine levels. DAC 24 would be highly linear if all signals y1[n] . . . y8[n] had identical high and low levels and if summing amplifier 31 were to amplify all eight inputs equally when generating y[n]. But it is difficult to balance a summing amplifier 31 and to match a set of DACs 30 with sufficient precision to avoid significant nonlinearity in the relationship between x[n] and y[n]. However, a dynamic digital encoder 20 can shape the DAC's error due to component mismatches so that frequency components of output signal y[n] resulting from component mismatch reside outside a pass band of interest so that that a pass band filter can remove them from y[n] or any signal derived from it.
A “non-dynamic digital” encoder will always map each value of x[n] to the same value of its output word {x1[n] . . . x8[n]}. For example a non-dynamic digital encoder might always map x[n]=5 to {x1[n] . . . x8[n]}={00011111}. In contrast, dynamic encoder 20 maps x[n]=5 to any one of many possible values of {x1[n] . . . x8[n]}. Four successive instances of input data x[n]=5 might result in four different successive values of word {x1[n] . . . x1[n]} such as for example {01001111}, {11010110}, {01110011}, and {11011100}. Since all of these values of bitset {x1[n] . . . x1[n]} have the same number (5) of bits set to a 1, summing amplifier 31 will drive output signal y[n] to the same nominal level in response to each bit set. But, when the 1-bit DACs 30 of FIG. 3 do not perfectly match one another, each of these values of bit set {x1[n] . . . x8[n]} can result in a slightly different value of y[n]. Dynamic digital encoder 20 therefore does not eliminate the error in y[n] due to the non-linearity of encoder but, when properly designed, it can vary bit positions of the 1's in its output word {x1[n] . . . x1[n]} in such a way that the error affects only high or low frequency components in y[n] that a subsequent processing stage can filter out.
An ideal dynamic digital encoder 20 appropriately shapes the error spectrum of output signal y[n] due to element mismatch using minimal hardware and produces its output word {x1[n] . . . x8[n]} with minimal path delay, thereby helping to minimize the total path delay through DAC 24. The path delay through a DAC 24 limits its operating frequency and can therefore limit the operating frequency of any sigma-delta converter having the DAC as a component. Designers have developed various architectures for dynamic digital encoders, each implementing a different dynamic element matching (DEM) technique, such as for example data weighted averaging (DWA), vector feedback, butterfly shuffling, and tree structuring, all of which are discussed in the paper “Simplified Logic for First-Order and Second-Order Mismatch-Shaping Digital-to-Analog Converters” by Welz et al, published in IEEE transactions on Circuits and Systems-II: Analog and Digital Signal Process, Vol. 48, No. 11, November 2001, incorporated herein by reference.
FIG. 4 illustrates an example prior art “tree-structured” dynamic digital encoder 32 as taught by Welz et al. Encoder 32 employs a tree-like network of switching blocks Si,j for systematically converting an N+1 level data x[n] that may have any integer value between O and N (inclusively) into a set of N bits {x1[n]-xN[n]} wherein the number of bits in the output bit set that are a “1” matches the current value of input data x[n]. The value of N may be any power of 2. For any value of N, encoder 32 requires b=log2(N) layers of switching blocks Si,j with each layer i consisting of 2b−i switching blocks Si,j. In the example of FIG. 4, N=8 and b=3. Each switching block Si,j is called a “radix-2” switching block because it produces two digital output words in response to a single digital input word. The sum of values of its two digital output words equals the value of its digital input words.
FIG. 5 shows an example of one way DEM circuit 32 of FIG. 4 might set bit states of output word {x1[n] . . . x8[n]} in response to an input word x[n] having a value 5. The top layer (layer 3) switching block S3,1 distributes its input value 5 to its two outputs as values 2 and 3. Layer 2 switching block S2,1, distributes its input of value 2 to its two outputs as values 1 and 1, and layer 2 switching block S2,2 distributes its input of value 3 to its outputs as values 1 and 2. The distribution process continues through layer 1 with switching blocks S1,1 . . . S1,4, distributing their respective inputs to their outputs as shown to produce an output word {x1[n] . . . x8[n]}={10101011} having five 1's.
Each switching block Si,j does not always allocate an input value in the same way each time it receives that input value. For example when a switching block Si,j receives an input value x[n]=5, it might allocate a 3 and a 2, respectively, to its first and second outputs but later, when it next receives an input value x[n]=5, it might allocate a 2 and a 3, respectively to its first and second outputs. By varying the manner in which they allocate their input values, switching blocks Si,j vary the manner in which encoder 32 maps input word x[n] to output word {x1[n] . . . x8[n]}. Thus although encoder 32 will always respond to x[n]=5 by producing an output word {x [n] . . . x8[n]} having five 1's and three 0's, the 1's will not always be in the same bit positions.
Each switching block Si,j can be implemented as a state machine. Its current input value and its current state together determine how it allocates its current input value between its two outputs. The nature of the algorithm each switching block Si,j implement affects the nature of the mismatch shaping encoder 32 provides, and many suitable algorithms have been proposed. One efficient algorithm tries to evenly distribute the switching block's input to its two outputs. For example when its input is an even number, a switching block Si,j evenly allocates its input value between its two outputs such that, for example an input value of 4 always results in an output data set {2,2}, or an input value of 6 always results in an output set {3,3}. When its input is an odd number, a switching block Si,j makes one output exceed the other by 1 such that, for example, an input of 5 will produce an output set {2,3} or {3,2} and an input of 1 will result in an output set {1,0} or {0,1}. Each switching block Si,j eliminates the average imbalance between its first and second outputs over time by:                1. setting the first output higher than the second in response to an odd input data value when it last set the second output higher in response to an odd input value, and        2. setting the second output higher than the first in response to an odd input data value when it last set the first output higher in response to an odd input value. For example, when a switching block Si,j receives an input sequence [5, 2, 4, 3], its output sequence may be [{3,2}, {1,1}, {2,2} and {1,2}]. Note that for the first odd input (5), switching block Si,j produces output set {3,2} such that its first output exceeds its second output by 1. To compensate for this imbalance when the second odd input (3) arrives, switching block Si,j makes its output set {1,2} so that the second output exceeds the first output by 1, thereby compensating for the previous allocation imbalance. FIGS. 5 and 6 show how encoder 32 of FIG. 4 might set bits of output word {x1[n+1] . . . x8[n+1]} when successive words x[n] and x[n+1] both equal 5. Note that both output bit sets in FIGS. 5 and 6 have five “1” bits, but they do not occur in the same bit positions.        
When the value of N is large, encoder 32 needs log2(N) layers of radix-2 switching blocks Si,j and the path delay between its input and output words increases with the number of switching block layers, thereby limiting the operating frequency of any DAC employing encoder 32. What is needed is an improved tree-structured dynamic encoder for an N+1 level DAC that requires fewer than log2(N) switching block layers so that the DAC can operate at higher frequencies.